(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices and more particularly, to a novel process and structure for making packaging substrates for wire bonded semiconductor devices.
(2) Description of the Prior Art
When the dimensions of the Integrated Circuits are scaled down, the cost per die is decreased while some aspects of performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, the approach has been taken to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines.
Increased Input-Output (I/O) combined with increased demands for high performance IC""s has led to the development of Flip Chip Packages. Flip-chip technology fabricates bumps (typically Pb/Sn solders) on Al pads on chip and interconnect the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package medium through the shortest path. These technologies can be applied not only to single-chip packaging, but also to higher or integrated levels of packaging in which the packages are larger and to more sophisticated substrates that accommodate several chips to form larger functional units.
The flip-chip technique, using an area array, has the advantage of achieving the highest density of interconnection to the device and a very low inductance interconnection to the package. However, pre-testability, post-bonding visual inspection, and TCE (Thermal Coefficient of Expansion) matching to avoid solder bump fatigue are still challenges. In mounting several packages together, such as surface mounting a ceramic package to a plastic board, the TCE mismatch can cause a large thermal stress on the solder-lead joints that can lead to joint breakage caused by solder fatigue from temperature cycling operations.
Prior Art substrate packaging uses ceramic and plastic Ball Grid Array (BGA) packaging. Ceramic substrate packaging is expensive and has proven to limit the performance of the overall package. Recent years have seen the emergence of plastic substrate BGA packaging; this type of packaging has become the mainstream design and is frequently used in high volume BGA package fabrication. The plastic substrate BGA package performs satisfactorily when used for low-density flip chip Integrated Circuits (IC""s). If the number of pins emanating from the IC is high, that is in excess of 350 pins, or if the number of pins coming from the IC is less than 350 but the required overall package size is small (resulting in a solder ball pitch of less than 1.27 mm.), the plastic BGA structure becomes complicated and expensive. This can be traced to the multi-layer structure used to create the plastic BGA package. This multi-layer structure for the plastic BGA interconnect package is referred to as the Build Up Multilayer or BUM approach and results in a line density within the package of typically 2-3 mil or 50 u-75 u range. This line density is not sufficiently high for realizing the fan out from the chip I/O to the solder balls on the package within a single layer. This leads to the multi-layer approach. The multi-layer approach brings with it the use of relatively thick (50 u-75 u) dielectric layers, these layers have a TCE (Thermal Coefficient of Expansion) that is considerably higher than the TCE of the laminate board on which the plastic BGA package is mounted. To counteract this difference in TCE""s the BUM layers must be (thermally and mechanically) balanced on the other side (the side of the board that does not usually require an interconnect density provided by the BUM layers) of the laminate board. This latter requirement results in the use of additional material and processing steps to apply these materials, increasing the cost of the BGA package and creating a yield detractor.
Another approach is the use of a flexible film as the starting material. A polymer film, such as the polyimide film or an epoxy based film of 2 to 3 mil thick with or without a copper layer attached to it, is processed by metalization and patterning on one or both sides. A completed two metal layer film, described as a layer pair, can be used as a packaging substrate material. Subsequent dielectric and copper layers can be build up on the processed first metal layer, such as the RCC (Resin Coated Copper) approach. Alternatively, two or more layer pairs can be bonded together to make a multilayer structure. The advantage of this approach is that it uses a minimum amount of material. However, because of the lack of stability of the film, the line and space density is limited to that of the BUM structure described herein, which is not sufficiently high for the high density packaging that is used to achieve a low cost substrate, having only a few interconnect layers.
Other Prior Art applications use thin film interconnect layers for flip chip or wire bond packaging substrates. These applications start with a laminate substrate onto which the thin film layers are deposited. For these applications, the laminate substrate is used as a base carrier substrate and provides the mechanical support. Plated Through Holes (PTH) are mechanically drilled through the laminate substrate and are used to establish connections to the backside of the substrate for solder ball attach and electrical contacts. By using thin films, high wire density and very thin dielectric layers can be realized. This approach also does not, unlike the BUM approach, require to counter-balance thick layers of dielectric in order to establish dimensional stability. A disadvantage of the laminate substrate is that the process of mechanically drilling holes through the laminate substrate is time-consuming thereby adding cost to the process. Further, the planarity of the laminate substrate does not meet planarity requirements for the deposition of thin films. Good planarity for the surface of the laminate substrate is established by depositing dielectrics and metal layers on the initial surface of the laminate structure, steps that again add to the processing cost of the BGA structure. Since the laminate substrate is composed using organic materials, the substrate is not dimensionally stable resulting in warpage and dimensional variations during high temperature processing and wet chemical interactions. This results in additional processing complications and costs.
The invention teaches a novel process and structure for creating packaging substrates that are used for wire bonded semiconductor devices. As such, the process and package of the invention are similar to previous high-density flip chip BGA packages. The term BGA of the invention refers to the ball grid array that is connected to for instance a Printed Circuit Board but where the contact balls of this array are connected to a (wire bonded) IC device via a substrate that is created by the process of the invention.
U.S. Pat. No. 5,509,553 (Hunter, Jr. et al.) shows a (3) metal layer process (DEMR) (see FIG. 5A) that appears to comprise a) sputter plating base b) plating metal (semi-additive plating), see col. 2.
U.S. Pat. No. 5,830,563 (Shimoto et al.) discloses a laminate substrate with thin films deposited thereon.
U.S. Pat. No. 5,837,427 (Hwang et al.) shows a (4) BUM process for a PCB.
U.S. Pat. No. 5,724,232 (Bhatt et al.) shows a package with a (1) metal substrate.
U.S. Pat. No. 5,525,834 (Fischer et al.) shows a package having a Cu substrate, thin dielectric layers (1-25 um thick) and thin dielectric layers (12 to 75 um), see col. 7 and 8.
U.S. Pat. No. 5,877,551 (Tostado et al.) discloses a package having a metal substrate with (2) dielectric layers formed of polymers, epoxy (3 to 100 um), see col. 4.
U.S. Pat. No. 5,485,038 (Licari et al.) teaches a package using a photo-imagable epoxy dielectric layer.
A principle objective of the invention is to provide an inexpensive and reliable method for high-density wire bond semiconductor device manufacturing.
Another objective of the invention is to provide a wire bond device package that significantly improves the cooling of the Integrated Circuit device that is mounted therein.
Another objective of the invention is to reduce performance limitations imposed by Prior Art high-density wire bond semiconductor manufacturing techniques.
Yet another objective of the invention is to provide for high pin fan-out for wire bond semiconductor devices.
Yet another objective of the invention is to eliminate the need for counter-balancing the effects of thick layers of dielectric used in conventional high-density wire bond semiconductor device manufacturing.
Yet another objective of the invention is to provide a method of packaging high density wire bond semiconductor devices by using Build Up Multilayer (BUM) technology in combination with thin film deposition techniques.
Yet another objective of the invention is to provide an initial surface with good planarity for the creation of high-density wire bond semiconductor structures.
A still further objective of the invention is to provide a structure devoid of warpage and dimensional variations during high temperature or wet chemical processing for the creation of high-density wire bond semiconductor structures.
In accordance with the objectives of the invention a new method is provided for mounting high-density wire bond semiconductor devices. The invention starts with a metal panel (also referred to as the metal substrate); a layer of dielectric is deposited over the first surface of the metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect patterns. The BUM technology allows for the creation of a succession of layers over the thin film layers. Each of the BUM layers created in this manner can be created for a specific function such as power or ground distribution and signal or fan-out interconnect. The combined layers of thin film and BUM form the interconnect substrate.
One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the wireable metal pad underneath the dielectric is exposed within the perimeter of the cavities. In addition, a metal die pad underneath the dielectric is partially or completely exposed to facilitate die attach and heat removal. One or more semiconductor die are inserted into the substrate cavity and are wire bonded to the openings that have been created in the layer of dielectric.
After the fabrication of the metal panel is complete, each substrate on the panel is tested. The substrates are singulated from the panel by cutting. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.